Lesson 5 – Designing with AXI using Xilinx Vivado – Part II
In this video I bring more practical examples of how you can create an AXI based sub-architecture including some AXI slaves, AXI masters and AXI Interconnect.
I Introduce the Xilinx AXI Central DMA Controller component and I used it in the example. I focus on the key points of defining suitable address maps for the components residing on an AXI interconnect. I also try to give a preview of some of the potential problems.
Then I show how you can convert your Block Design inside Vivado into a Packaged IP and how you can instantiate it in another project.
Presentation : designing_with_axi_in_vivado_part_ii
Video : Watch Online
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Your videos are really great! The best material I found so far about AXI interfaces and an awesome resource to get started with building custom IPs / interface them. Keep going, I’m really interested in further videos, specifically in AXI stream interface informations.
Thanks for sharing your knowledge 🙂
Hello, thanks for the great video and detailed explanations – Xilinx should hire and donate to you to make more tutorials.
Question : I followed along your video in Vivado 2014.3, when I create the HDL wrapper or validate the design, I get a critical warning message (11x the same message), telling me that “the reset pins are connected to an asynchronous reset source (asynchronous to the associated clock). This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /ACLK”
Is this something that ‘can’ be ignored- if you run automated connect, the Processor System Reset module is added automatically. But maybe, as you’re designing a subcomponent here, the synchronous reset will be generated at the Top Level ?
same problem
Hi, the series of videos are really helpful. Thank you very much!
I meet the same problem with Ronny’s, that when I validate the design, I get critical warning messages, telling me sth like “the reset pins are connected to an asynchronous reset source (asynchronous to the associated clock aclk)”.
Would you please tell me if this will be problem?
Hi Guys, Thanks for your interest. OK, I will explore this issue more, just I have a question for you. Why don’t you add the “Processor System Reset” block to your design as the tool is suggesting? In your block design, where you put your created IP and you integrate it into the rest of your design, you can also very easily add this block. (if the tool did not add it itself). I think that should solve the issue.
Your videos really helped to get started with Vivado, thanks, i wan more of them related to HLS design.
well, thanks for your kindness, and soon i will start to add videos on doing designs with high-level synthesis.
I tried doing this but for a minized. i get the error that my IO placement failed due to over-utilization. Is there any way to fix this?