Lesson 8 – An Overview on ZYNQ Architecture
This session is a brief overview of the architecture of Xilinx ZYNQ device. It tries to talk about why this architecture can be useful for many computational tasks. It shows the internals of the ZYNQ Programmable System (PS) briefly. It discusses the AXI interfaces between the PS and the PL in the ZYNQ device. Furthermore, it looks at the most important documents available for the ZYNQ device. The ZYNQ PL is also discussed briefly. For this session there exist four videos. Three are created at the studio of Electrical engineering department and the other is my screen cast. each of…
Estimating Power at RTL using Synopsys Design Compiler
Estimation of power consumption of an integrated circuit at RT level can be handy since it allows designers to obtain an approximate and yet accurate enough estimate on total power consumption of their design in a very short time. Basically, the designer runs the logic simulation for his pure RTL design and obtains the switching activity statistics for his circuit. The test bench developed by the designer for the logic simulation is indeed the workload imposed to the circuit and power will be estimated for this specific workload. In this writing I go through the details of how power estimation…