So the guys have created this marvelous looking board : Paralela the board!

In this post, which I update gradually I will try to describe why using this board is not a correct decision!

First look, the board is amazing ! 18 CPU cores, mind blowing! The thing they don’t tell you is that 16 CPU cores on the Epiphany processor do NOT have direct access to the DRAM memory!

Indeed this is why the ZYNQ is there, to act as a bridge between the DRAM-less epiphany and the DRAM memory. This introduced memory access latency for performing calculations on the Epiphany side however, will kill the performance of many memory-hungry computational algorithms.

Now another funny thing with this board is that they have put the JTAG interface on the pins of the PEC connector at the back of the board. This means when you buy the board you don’t have normally access to the JTAG. As a FPGA developer imagine with yourself that some one has given you a board (even a ZYNQ board) without access to JTAG! How do you feel? Now the more you have gone through challenging FPGA design projects the more you will get nervous! Your most important debugging interface is missing!

You want the JTAG back? You should buy a break-out board, which costs almost the same price as the main Parallela board itself! Only after that you will have the set of JTAG pins available which you can connect to your JTAG cable! Did you buy Parallela because it is cheap? Now you pay its price twice! 😉

The question I really want to ask these guys is why shouldn’t we bring out the jtag interface as a normal 5 pins header?