Lesson 13 – ZYNQ PL Reconfiguration
During this lesson we try to focus on the concept of reconfiguration. This feature in FPGA devices is extremely useful since it allows the user at each point in time to reconfigure his FPGA fabric according to the incoming workload and computational and interfacing constraints. First we focus a very basic use case: reconfiguring the ZYNQ PL with a set of bitstreams stored on the SD card. We show the steps required to create a system which allows the user to reconfigure the PL whenever he wants with each of the bitstreams available on the SD Card. Watch video: Online…
Lesson 12 – AXI Memory Mapped Interfaces and Hardware Debugging
So far we have been talking mostly about AXI stream interfaces. Now it is the time to have a look at AXI memory mapped interfaces. We begin with a brief look at the signals which create an AXI memory mapped interface. Then we create an example design and with the aid of hardware debugging tool which is integrated into Vivado we take a look at how these signals interact with each other during a read or a write transaction. This lesson is created at the professional video recording studio of TU Kaiserslautern and belongs to the Microelectronic Systems Design Research…
Lesson 11 – Booting Linux on the ARM host of ZYNQ
So far we have shown our example designs on the ZYNQ device using a bare-metal system for the ARM CPU cores. In this lesson we focus on the procedure through which the Linux operating system can be run on the ARM cores of the ZYNQ. We try to show every possible option for bringing up Linux on the ZYNQ. We then create a simple hardware, consisting of two GPIO units implemented on the PL. For these hardware units we develop a Linux kernel level driver, along with its user level application, so that we can write to these hardware blocks…
Lesson 10 – AXI DMA in Scatter Gather Mode
During previous lesson we learned how to use AXI DMA unit to transfer data from an AXI Stream Master to an AXI Memory Mapped slave port. We showed how AXI DMA can be programmed in order to perform the required transfer task. We did this with the ZYNQ device and we practically showed examples on the ZED board. In the previous lesson, whenever we want to perform a data transfer using AXI DMA we should program it. Thus for every transfer the CPU should program the AXI DMA. But some times, the required sequence of transfers are known and we…
Lesson 9 – Software development for ZYNQ using Xilinx SDK (Transfer data from ZYNQ PL to PS)
During the previous lessons, we described the basic concepts of AXI interfaces and then we talked about AXI Stream interfaces in more detail. We showed how you can create your own custom AXI Stream units by using Vivado HLS or by directly creating the design using Verilog. After AXI Stream interfaces, it makes sense to go towards more complicated AXI memory mapped interfaces however, I have decided to first focus on software development for the ARM host of the ZYNQ device. During these the videos in this lesson, we will go through how you use the Xilinx SDK environment to…
Lesson 8 – An Overview on ZYNQ Architecture
This session is a brief overview of the architecture of Xilinx ZYNQ device. It tries to talk about why this architecture can be useful for many computational tasks. It shows the internals of the ZYNQ Programmable System (PS) briefly. It discusses the AXI interfaces between the PS and the PL in the ZYNQ device. Furthermore, it looks at the most important documents available for the ZYNQ device. The ZYNQ PL is also discussed briefly. For this session there exist four videos. Three are created at the studio of Electrical engineering department and the other is my screen cast. each of…
Lesson 7 – AXI Stream Interface In Detail (RTL Flow)
In this lesson we continue our exploration of AXI Stream Interfaces. We choose a pure RTL design approach during this lesson. We use the Vivado's "Create and Package IP" capability to create a simple unit which contains one AXI stream master interface and another custom general purpose interface. We go through the RTL source code of the design, and we change the RTL produced by vivado to add our own customizations. In another example, we create a design containing two AXI stream input interfaces and one AXI stream output interface this time using Vivado and in Verilog. At the final…
Lesson 6 – AXI Stream Interfaces In Detail (HLS)
In this lesson we focus on AXI stream interfaces. We use the Vivado HLS and create a set of example designs. The first one is a simple counter which sends the count values over its AXI stream master interface. The next example is the counter but with an additional AXI stream slave interface through which one can configure the counting range of the counter. Finally we create a module which contains one General Purpose I/O (GPIO) input and one AXI stream master output. The module receives the data over GPIO and sends them through the streaming interface. For each of…
Lesson 5 – Designing with AXI using Xilinx Vivado – Part II
In this video I bring more practical examples of how you can create an AXI based sub-architecture including some AXI slaves, AXI masters and AXI Interconnect. I Introduce the Xilinx AXI Central DMA Controller component and I used it in the example. I focus on the key points of defining suitable address maps for the components residing on an AXI interconnect. I also try to give a preview of some of the potential problems. Then I show how you can convert your Block Design inside Vivado into a Packaged IP and how you can instantiate it in another project. Presentation…
Lesson 4 : Designing with AXI using Xilinx Vivado
In this lesson we demonstrate a practical example in which we use the Xilinx Vivado environment and we create a sample AXI based architecture. This lesson shows the primary skills of designing with AXI under Vivado environment. As our main AXI master, we use the Microblaze CPU core. Then we add several different AXI slave components to the system. The purpose is to show how these AXI based components get connected to each other inside the Vivado environment. The purpose is not to build a fully functional system. This lesson contains a presentation, a Vivado TCL script (Gzipped tar format)…