ZYNQ Ultrascale+ and PetaLinux (part 15): rootfs on SD card with X and Qt libraries
We configure PetaLinux to have its root file system on the second partition of the SD card. We then go through the steps required for preparing the SD card, creating disk partitions, formatting them and copying required PetaLinux files to each of the partitions.
ZYNQ Ultrascale+ and PetaLinux (part 14): Build with X and Qt Libraries enabled
We use Xilinx BSP provided for ZCU104 to build PetaLinux with the X (graphical user) environment enabled. We also customize PetaLinux root file system to include Qt Libraries. We then build the SDK that we need later for building Qt applications.
ZYNQ Ultrascale+ and PetaLinux (part 13): Graphical User Interface and Qt Applications (i)
In this video we start looking at bringing up PetaLinux with its graphical user interface (X server) enabled. We talk briefly about the GPU block available inside Zynq ultrascale+ EG and EV devices. We briefly describe our flow for compiling petalinux. We show the primary view of our user application in Qt.
ZYNQ Ultrascale+ and PetaLinux (part 12): FPGA Pin Assignment (LVDS Data Capture Example)
In this video we go through a simplified example design which transfers data between two chips at a total rate of ~ 5 GBits/s using LVDS signals. We look at how pin locations can affect the final timing of the design.
ZYNQ Ultrascale+ and PetaLinux (part 11): FPGA Pin Assignment (PCIe example)
We continue with our simple PCI Express design example in this video and we show two different pin assignment scenarios for this design. We show how pin assignment can affect the quality of the place and route in the design.
ZYNQ Ultrascale+ and PetaLinux (part 10): FPGA Pin Assignment (with brief look at LVDS and PCIe)
First section of the video on Pin assignment. We look at pin assignment done for our ZCU104 based vivado project. We try to cover other topics briefly as well, we look at MIPI CSI2 RX IP as an example case, we also do pin assignment for a X4 Gen3 PCIe interface. We briefly talk about each of the High Density and High Performance IO Banks. This video is to be continued on the next part.
ZYNQ Ultrascale+ and PetaLinux (part 9): nVidia Jetson AGX Xavier SPI & Xilinx ILA (Section 2)
NOTE: At nVidia Jetson side, the screen capture frame rate was very low. So in the video you will see the parts I am showing Jetson screen at a lower frame rate. Part 9 Video
ZYNQ Ultrascale+ and PetaLinux (part 8): nVidia Jetson AGX Xavier SPI & Xilinx ILA (Section 1)
Part 8 has 2 sections, each section in one video. We look at setting up the SPI Interface of nVidia Jetson AGX Xavier. We describe the hardware setup and the experiment we want to perform. We briefly look at System ILA IP at our ZCU104 vivado project Part 8 Video
ZYNQ Ultrascale+ and PetaLinux (part 7): Folder structure, Vivado Projects (SPI, IIC,…)
Welcome to part 7 of ZYNQ Ultrascale+ and PetaLinux videos. In this video we briefly describe the folder structure of deliverable package for these video series. We go through the Vivado projects for both of the ZCU104 and ZED boards. We describe the design architecture. We talk about the custom AXI Slave SPI cores. We produce the bitstream and XSA files for both of the board projects. These will be used for the coming videos. Video Part 7
ZYNQ Ultrascale+ and PetaLinux (part 6): recap, updates next steps
Part 6 of the series about running PetaLinux on ZYNQ Ultrascale+. The updated hardware architecture is shown in this video. It contains the following 3 boards: 1) NVIDIA Jetson AGX Xavier 2) Xilinx ZCU104 3) Digilent ZED board I briefly discuss the architecture that we want to implement and our goals. These series will continue. Jetson, Xavier are trademarks of NVIDIA. ZYNQ, ultrascale are trademarks of Xilinx. Video Part 6