Lesson 9 – Software development for ZYNQ using Xilinx SDK (Transfer data from ZYNQ PL to PS)
During the previous lessons, we described the basic concepts of AXI interfaces and then we talked about AXI Stream interfaces in more detail. We showed how you can create your own custom AXI Stream units by using Vivado HLS or by directly creating the design using Verilog.
After AXI Stream interfaces, it makes sense to go towards more complicated AXI memory mapped interfaces however, I have decided to first focus on software development for the ARM host of the ZYNQ device.
During these the videos in this lesson, we will go through how you use the Xilinx SDK environment to create your own software running on the ARM Cortex A9 cores of the ZYNQ. We look at how this software will interact with the units that you have on the ZYNQ PL.
As an example case, we focus on AXI DMA unit. As described in previous videos this unit is responsible for receiving AXI Stream data and putting them on the shared DRAM memory of the PS. So basically it is an AXI Stream to AXI memory mapped interface converter. We go through how we can program this unit using the ARM host.
During the videos of this lesson, we use the ZED board to practically evaluate the correctness of our design.
Presentation (Prezi) (under update) : View Here
Video Part I : Watch Online.
Video Part II : Watch Online.
Video Part III : Watch Online.
Video Part IV : Watch Online.
Video Part V : Watch Online.
Video Part VI : Watch Online.
Video Part VII : will be added soon.
Please make a donation if the videos have been useful for you.
(The source codes for this lesson are available upon a donation)
Thanks so lot Mohammad. I probably didn’t search well but couldn’t locate some beginner examples to do basic PL/PS data exchanges using Vivado, so your series is most welcome.
BTW I saw in your projects list the Windows CE BSP one. The Microsoft .NET MicroFramework source code is freely available and even though managed code is interpreted, I think it’s nice also to be able to develop high-level apps with C# under Visual Studio while another core can run real-time native code and with a FPGA on top.
Just starting with Zynq but here’s a glimpse of the first NETMF test on the Zynq:
http://www.youtube.com/watch?v=YxAgC30m-Ac&list=UUnbByTE3epXgaJ4lsGi31Nw
But first thing first, I now want to be as comfortable with the AXI stuff as breathing.
Many thanks again,
patc.
this video is unavailable
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Many thanks for posting this. When are you going to post more lessons?
hello!
Many thanks for posting this, but I want to know one thing.
How do i transfer data from ps to pl (using the amba bus-not the DMA).
i cant found the answer for this.
like maybe i have function which saing “SendDatatobus(data,addr)”
something like that?…
thank you
idan
Yeah, there are couple of ways you can do that.
First, the simplest, you write data through either GP0 or GP1 to the PL. We have created a video on that, which soon we will put on
Microelectronic systems design research group of TU Kaiserslautern, in you-tube.
Another method, you put the AXI DMA and then you use its AXI MM to AXI Stream connection.
Programming is very similar to what I have done for AXI S to AXI MM.
Then you can transfer data from any of HP ports to the AXI Stream output.
Now if you also need on the other side the data to be available with address (not as a stream) then the AXI Central DMA is a good option.
hello sir
i practiced your design in sdk.
but when i run the command mrd 0xa000000 10
i am not getting the proper value. it is showing some garbage values , it is not counting properly.
can you suggest me some solution.
thank you
Hi. I think we had this discussion before.
First, as I show you practically on the video, you should not get garbage, there should be some data transfered. Now it is not doing the transfer, you should double check your program and design.
Second, as I said the sample generator code has a small bug, which I fixed and if you have it, it should work fine since we have used it in more serious projects.
Hey sir!
would you please send me the final version of your sample generator to me per email.
I have the same problem with shivendra joshi, and i have double checked the programm, and it could not work correctly.
thanks alot!
Rui Ma
Dear Rui,
the latest versions are always available in the dropbox folder.
hello sir,
I have same problem as Rui Ma. So, please can you tell me how to access your dropbox.
Princy Teli
hello sir,
I have same problem as Rui Ma. So, please can you send me how to access the dropbox.
Thanking you,
Princy
Hi Mohammad,
Can you please share the dropbox folder link with me ?
Best regards,
Balcic
write me an email
Hello sadri;
I am also working on fpga in Germany. I also want to how i can transfer data from ddr to Ethernet. Previously i transfer udp packet using tri mod Ethernet core. for this purpose i use PL for udp packet parameter declaration. I am confuse now where i design udp packet and how i canroute data from ddr to Ethernet core. Need your suggestion…
Hello currenyly have the same challenge. Did you accomplish it?
Hi guys, I have the same issue. Would you mind sharing with me a few suggestions on the best approach?
Regards,
Irida
Hi Guys,
If you can share something about same issue, I ll we very thankfully to you.
Regards,
Saban
I am testing your design on Zynq MMP
When I run the dow command with Hello_World.elf, I get following error
Cannot access DDR: the controller is held in reset
Any idea why this is happening?
if the PS is not initialized through calling ps7_init, the DDR stays in reset.
Even i’m facing the same problem, do you have any remedy for that. What to for making PS to be initialized.
hi
is there any way to run thease program without having zed board.
is there any simulator exist??
thanks
Hi Ali,
I am preparing very low cost ZYNQ boards that every one can afford. So soon (very soon) you can have your own.
Is there any simulator for ZYNQ? Yes, there is a virtual platform developed by Cadence, which resembles the operation of a complete ZYNQ device.
Said that, I prefer to use the real board since access to that virtual platform is way harder than to purchase the device.
Stay tuned!
Hi Mohammand, I am Looking forward to your board. Let me know when it is available. Thanks 🙂
Hi Mohammad
currently I enjoy your video. You tell slowly all important details of your thoughts and design. This is very helpful in cases someone had no chance to do it by themself in the past.
From your video #4 of lesson 9 here I saw something I didn’t understood: Your packet size was 256 and you wrote to address 0xa000000. Why the address from 0xa000000 to 0xa000083 is modified only? It looks that you only write 132 bytes of data … is this the error of the generator you are talking of (because I wonder you tell shivendra joshi which gets garbage at all this is from the bug. It can be this or that but not both, eh?) It seems that the DMA is not working as expected …
Keep going on and thanks for all!!!
/Jesko
hi. the dma works fine. look at my videos on dma scatter gather mode. as you see every single byte can be transferred fine.
Hello sir I am a big fan of your teaching and i have a few questions
1) are the videos and the notes of your lectures by you and what your student noted down are available in English???
2) I have one more doubt that is in lesson 9 toward the last session in the demo when we transfer the set 256 bytes of data which is to be transferred by the AXI_DMA to the DRAM and once it is done then the AXI_DMA sends an interrupt to the ZYNQ PS that it has finished transferring the 256 data and will transfer the next set of 256. Now my question is what about the next 256….
3) In my xmd console it shows all the first 256 that but it does not show me the next set of 256. For simplicity i havent changed any addresses that you have shown us in the C program. In my XMD console it show that it does the first transfer but after that the code that you wrote to generate the interrupt and then to transfer the next set of data is not working that is what i think I may be wrong please guide me. Please tell me what to do next ??
Thank you so much once again!!!
Prasad,
I had the same problem. First sample set is transferred but later sets are not. I included some debug codes[(xil_printf(“something..”)] to see if the statements in interrupt handler are working. I couldn’t get anything printed. Something seems not fine in the interrupt handling. May be I missed something from the video. But don’t know what it is.
Have you found the solution? If so pls post here.
Thanks
-Susantha
hello
thank you for these posts but i don’t understand how communicate between ps and pl.in addition to how to drive frame size by axi gpio’s .and another qustion :are you have a simple example for uart communication in zynq by pl and ps communication.
thanks
hello sir,
I have same problem as Rui Ma. So, please can you send me how to access the dropbox.
Thanking you,
Princy
Hi dear Dr. Sadri
I am writing to thank you for your great ZYNQ training videos.
I don’t access to any ZYNQ-related board at the time of speaking.
You said that VCS simulator is powerful in the meantime light
environment to consider the result of code from VIVADO or even better
than the simulator of VIVADO. But I was wondering if I could consider
the signals of the PS part that are coded in SDK Software too.
Could you please give me some advice that will help me simulate PS
part too? is there any limitation of using simulator environments?
By the way i am a windows7 user.
Thank you
Best regards
Ali karimi
Tehran / Iran
Ali! if you do not have a hardware board and you want to simulate a zynq or zynq ultrascale mpsoc, the best tool is the simulation environment developed for zynq by cadence. I do not remember the exact name however, it is there in the cadence web site. it is a complete model of zynq.
Mr. Sadri,
I have a question, im sure there’s a simple answer. So my project is a Still image convolution engine implemented on an Zedboard. I am reading pixel values using a DMA from PS to PL (at this point is stream data) then putting this data into fifo stream buffers, storing snapshots of 7×7 size matrices in DRAM and performing the convolution operation (multiplication, addition then division) on this 7×7 matrices and the kernel matrix. I then send this data back to the DMA to be written back to DDR. My question is when i read stream data from the DMA and want to do the convolution operation on it, i cant (I want to use the DSP slices for fast computation). How can I perform computation on Stream data is my question.
Your videos have helped me a lot, I have no experience in this area but your videos are giving me a good idea on how to proceed.
Hi Sainath, I think processing the incoming streaming data is very straight forward and a module for this can be simply written both in rtl (verilog or vhdl) as well as in HLS.
Hi Mohammad
Firstly thank you for your educational and helpful videos.I am an electrical electronical engineering student at Turkey.I did all the steps from beginning to lesson 9 part 4 I need source codes for SDK part and sample generator bug fixed code I know that I need to make donation for source codes but I am from Turkey and Paypal doesnt work Turkey anymore.Is it possible to have source without donation .I am sorry for not making a donation for your helpful videos.I will be very happy if you help me to have codes I need them for a serious hwproject
did your issue got solved?
Hi! Your videoes really helped me alot. Thanks!
One question though…
Tried this, and successfully transfer data from the sample generator. I have also tried filling a bram with counter values. A problem I am facing is when I try to read the contents of the ddr before dma-transfer (with the printf function). When I do this I read the same values (garbage) before and after dma transfer. When i skip this i read the counter values from the ddr. Any thoughts/suggestions on this?
disable cpu cache for that region. indeed, prohibit the cpu to read from cache for that address range.
Dr. Mohammad S. Sadri. Your tutorials are really helpful. I am new to the field of FPGA and am struggling with data acquisition for from ADC using Zedboard FMC (where I will have to use DMA). Going through your videos have really helped me a lot. Thank you very much. I hope you will make many more tutorials related to FPGA in the future.
From Dr. Sadri’s teaching video I learn more details. Now I know Verilog too.
How do you map the input of SampleGenerator to FMC pins? could you please show me just only 1 connection. Cheers
hi look at the board users guide, there is a map between fmc pins and fpga pins, use that for your pin location constraints inside your vivado project.
Hello,
your video on PL to PS was very useful.
Thanks
Hi Dr. Mohammad S. Sadri,
at part IV,
1. StartDMAtransfer(0xa000000, 256);
Why do you use 256 bytes in the function while the frameSize = 32 words, 4bytes / words = 128 bytes ?
After address A000080, (or 128 bytes), all are random. Am I missing something you taught?
A000000: 081C047C
…
A000078: 081C049A
A00007C: 081C049B
A000080: 081C049C
A000084: F77F29FE
A000088: FF7F1FE8
2. When does the interrupt output of hardware axi_DMA_0 take place ?
hi i do not remember what i have done there, this is around 2 years ago. however, lets say we have packets of 128 bytes, it is still possible to issue a transfer of 256 bytes, worth of 2 packets. and should work. interrupt comes after a transfer task is done.
hi ,sir:
I am sorry,I cannot donate to you,just because i am not use the Cridit Card(Just me).
I am a chinese,my english is so poor,but i think you can understand what i mean.If you use mobile payment,like “Alipay”，I am very gold to donate some to continue learn the video what you recorded.
And I had learned it serveral days.But i could not learn it due to I donnot have the other link.
So ,If i could get the link?
thanks!
Hi, Sadri
I want favor from you. This favor is about sample generator. Sample generator is not working due to versions differents. Please do you share sample generator with me. I want make to you donation but I’m a student and I don’t have enough money becous 1 dolar is equal 4,62 tl and I
only take monthly 100 tl 🙁
Hi Muhammad Please send me the source Code.
source codes are available upon a fair donation.
Hi,
great great videos. really!
I cant start even explaining how much help you provided me.
I am very keen on donating to get the source codes and would also like to donate some more for some tech support. Can you please contact me?
hi daniel. happy the videos have helped. i am gonna keep producing them. thanks for support. donations can be done in the donation section of googoolia.com.
I make a donation for session 9, How do I get to access your drop box?
i should have already shared your account coordinates with you.
How do is use the microphone on a minized board?
Hi Muhammad,have you done the project transfer data from PL to PS on linux platform ?
Yes. i have an educational package for that, but it is not free.
I am following your videos from lesson 1 to 9 (II) in this part I have created the same project as yours. But the following error I can’t solve please help.
Synthesis
Out-of-Context Module Runs
AXI_mapp_synth_1
[Synth 8-448] named port connection ‘En’ does not exist for instance ‘Sample_Generator_v1_0_S_AXIS_inst’ of module ‘Sample_Generator_v1_0_S_AXIS’ [“e:/NRTC/AXI_DRAM/AXI_DRAM.srcs/sources_1/bd/AXI_mapp/ipshared/86af/hdl/Sample_Generator_v1_0.v”:49]
[Synth 8-285] failed synthesizing module ‘Sample_Generator_v1_0_M_AXIS’ [“e:/NRTC/AXI_DRAM/AXI_DRAM.srcs/sources_1/bd/AXI_mapp/ipshared/86af/hdl/Sample_Generator_v1_0_M_AXIS.v”:4]
[Synth 8-285] failed synthesizing module ‘Sample_Generator_v1_0’ [“e:/NRTC/AXI_DRAM/AXI_DRAM.srcs/sources_1/bd/AXI_mapp/ipshared/86af/hdl/Sample_Generator_v1_0.v”:4]
[Synth 8-285] failed synthesizing module ‘AXI_mapp_Sample_Generator_0_0’ [“e:/NRTC/AXI_DRAM/AXI_DRAM.srcs/sources_1/bd/AXI_mapp/ip/AXI_mapp_Sample_Generator_0_0/synth/AXI_mapp_Sample_Generator_0_0.v”:56]
[Synth 8-285] failed synthesizing module ‘AXI_mapp’ [“E:/NRTC/AXI_DRAM/AXI_DRAM.srcs/sources_1/bd/AXI_mapp/synth/AXI_mapp.v”:13]
[Common 17-69] Command failed: Synthesis failed – please see the console or run log file for details
Which Sample generator I should use in this case? the 1st one or the later one?
Hi, i have a question, How did you measure the time of transferring the packets?
use ILA, to me thats the most accurate.
did i answer your question?
Hello Sadri,
I find these videos very very helpful and they have saved me a lot of time in my PhD.
May I know if there is any minimum donation amount set up in order to get access to the source codes??
Thank you.
i will update the donation page with more info
Dear Mohammad,
I am a master’s student.
First of all, thank you so much for all the great videos. I did a small and affordable donation(I know it is not comparable with your efforts), would you please let me have the codes of this lesson?
Looking forward to hearing from you.
Best regards
you have the sources now. to the best i remember.
Hello sir,
firstly thank you very much your videos. I have one dought related to gpio.In my project i am using two gpio cores and 1 gpio with 2 channels and 1 gpio with one channel and all channels are outputs.Using this gpio cores i am sending some cordinates from microblaze to custom ip core. So is there any particular way (or) approach to use this gpio cores to write sdk code.Like initialize , configure, set direction and discrete write like that.
best regards,
Jagan Mohan
Hi. You mean in Linux? or stand alone?
In both, it is pretty straight forward to use the GPIO.
In stand alone more , use functions like Xil_Out
In Linux, use the /sys/ entries for GPIO.
Hello,
I have appreciated for your article.
Now, Presentation link is failure.
Please, I hope you to upload document again.
Thank you in advance.
please write me an email from your univ account