Howto interact with Android GUI Under GEM5
Keywords : Android, GEM5, mouse tap, mouse move, touch point tap, touch point move , click This post is mainly answering this question: Is there a kind scripted , automated way, to perform mouse (touch point) movement, and mouse click, Inside Android, Running under GEM5? Problem Description: When you are running Android under GEM5, it is very slow. This makes user interaction with Android GUI difficult. some times for example, you perform a click and at the end you don't understand if the click operation has done or not, because, it takes a lot of time ( 5 minutes or…
Customizing ZYNQ uramdisk image
You have the file of the Linux for ZYNQ and you want to make modifications to it. 1- Copy it some where 2- strip out the first 64 bytes (which are mainly of u-boot) to obtain the compressed ramdisk dd bs=1 skip=64 if= of= 3- unzip the ramdisk gunzip 4- mount it some where sudo mount -o loop a 5- go to the a/ folder and make what ever modification you want and unmount it. sudo umount a 6- compress it gzip 7- make the final uramdisk again mkimage -A arm -T ramdisk -C gzip -d The important point :…
Ideas for Projects on Embedded FPGA design – 1
Many students write me regarding possible ideas to do projects using FPGAs. Here based on my experience in recent years and based on what I see more important, I list a set of ideas which can be considered as suitable and useful targets for doing projects on the Embedded FPGA design topic. First things first! Connectivity! Suppose that you have implemented a computational unit on the FPGA. The first question which raises is how do you connect this guy to the rest of the system so that you can use it efficiently? In fact, most of the times we have…
A System Level Approach to Multi-core Thermal Sensors Calibration
I am the second author of this paper. Paper presented at PATMOS11, Spain. The paper is mainly about calibration of thermal sensors in the Intel Single-chip Cloud Computer. The paper is available via springer.
Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer
I am the Second author of this paper! This paper is presented at, DATE12 conference, in Dresden, Germany. In this paper we use the Intel Single-Chip cloud computer as a test platform and we quantify the effect of frequency scaling of CPU cores on the execution speed and energy consumption of different parallel multi-core benchmarks. Download : DATE12_paper Abstract : Dynamic frequency and voltage scaling (DVFS) techniques have been widely used for meeting energy constraints. Single-chip many-core systems bring new challenges owing to the large number of operating points and the shift to message passing interface (MPI) from shared memory communication.…
Hetergeneous Multi-Core OpenRISC Cluster on Xilinx ZYNQ
During my final months of my stay in the ERC Multi-therman laborary in University of Bologna, I have implemented a heterogeneous computing platform using the Xilinx ZYNQ device. The platform is built mainly for the Xilinx XC7Z045 ZYNQ device. As of its current state, the platform contains two clusters on the PL connected to the ARM cores inside the ZYNQ-PS. Each cluster contains 4 OpenRISC 1000 cores.
Interests and Experiences
Research Interests - Heterogeneous Low-power Re-configurable architectures - Development of Kernel Level Software to support Hardware Acceleration in Hand-held devices. - Embedded Image/Video processing systems, stereoscopic and 3D vision. - Avionics, navigation, auto pilot systems Management and Leadership Experiences - Leading a team of 4 developers (All ), working on a complete, super fast, FPGA based computer, running embedded Linux, ICTI - Leading a team of 3 developers (All ), working on the design of unmanned air vehicle, Mechanical Engineering Department, IUT, 2008 - Leading a team of 7 developers (one , two , 4 ), building an FPGA based…
Single-Chip Cloud Computer Thermal Model
Paper presented at THERMINIC11 conference, Paris, 2011. This paper presents a thermal model for Intel Single-chip Cloud Computer. The thermal model is mainly based on Hotspot. Download : Sadri_THERMINIC11 Abstract : Spatial and temporal non-uniformities of workload and power consumption advanced Systems-on-Chip (SoC) platforms result in localized high power densities, which lead to temperature hot-spots, gradients and thermal cycles that may cause non-uniform ageing and accelerated chip failure. The Single-Chip Cloud Computer (SCC) is an experimental many-core processor created by Intel Labs and it integrates thermal sensors to track the chip thermal behavior. Unfortunately these sensors provide a limited introspection on…
3rd Year PhD Presentation
Here is my 3rd year PhD presentation which is basically a brief overview of what I have done during 3 years of PhD at Electrical Engineering and Information Systems Department of University of Bologna, Italy. Title : Temperature Variation Aware Energy Optimization in Heterogeneous MPSoCs Download : 3rd_year_presentation_sadri_brief ( Note : Using the contents of this presentation is ONLY ALLOWED with directly citing its authors. )
MiMAPT: Adaptive Multi-Scale Thermal Analysis at RT and Gate Level
The first paper related to MiMAPT software is presented at THERMINIC12 workshop, Budapest, 2012. This paper introduces MiMAPT, a tool that I developed to do thermal, power and timing analysis of integrated circuits while accounting for on-die temperature non-uniformity. Download Paper : sadri_therminic12 Brief : Tight timing/area constraints produce on-chip layouts with non-regular shapes for RTL entities. Thus, grid-like floorplans where RTL entities are abstracted as rectangular blocks for thermal simulation lead to inaccurate results. In addition, spatial and temporal variability of chip workload causes localized temperature variations. Exact localization of hotspots at gate-level necessitates an extremely detailed spatial resolution which is…