Lesson 3 : AXI Stream Interface
This lesson talks about the other kind of AXI interfaces : AXI stream
So far we were showing only AXI memory mapped interfaces however for most of the data-flow applications AXI Stream interface is the main mechanism to connect processing units together.
This lesson shows the principles of AXI stream interfaces, and talks about connecting AXI stream and AXI memory mapped devices together.
Presentation Download : axi_stream.pdf
Videos In English: What is AXI Interface? (Watch Online)
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Hi Mohammad,
Thank you very much for all the information that you share. I have watched all of your videos
and are looking foreward for more to come.
I have a question regarding page 9 “AXI Data Mover” of lesson 3.
I refer to MM2S part of the data mover (I guess the answer for the the S2MM part will be similar).
In the diagramm, there are two AXI interfaces: M_AXI_MM2S and M_AXIS_MM2S. I understand the
role of this two interfaces. When I try to rebuild this example with Vivado, I find
two more AXI interfaces on the IP: S_AXIS_MM2S_CMD and M_AXIS_MM2S_STS.
I guess, this are the interfaces that are used to communicate with the software running on the CPU.
When I look at the Zynq, I dont find matching AXI interfaces. How are the AXI stream interfaces of the
datamover connected to the processor? Is there a need for a “translation IP” or something?
greetings
Manfred
Hello Mandfred,
Thanks for your interest in Videos.
Yes! You are right. Those two are the command interfaces and they are AXI stream interfaces as well.
So if you are going to program the data mover from the PS (e.g. through GP0) then you need additional logic which receives the command from GP0 and writes it to the command stream interface. However if you are programming the data mover by the logic resided at the PL, then it is extremely easy to program the data mover since the interface is very simple.
Now if we want to program the data mover from the PS, the best I see to do is to create a simple custom IP which receives the command words from the Memory Mapped GP0 or GP1 AXI Master interfaces and generates suitable AXI stream signals transferring these command words to the AXI data mover. This is very easy and I will fully cover it in the videos.
Honestly speaking I am aware of the fact that there exist simpler modules than data mover from transferring stream data to dram memory and I have seen some people using that. But, once you got your AXI datamover running you can easily solve any kind of connectivity problem while keeping your throughput at a very high level.
Hello Mohammad,
“Now if we want to program the data mover from the PS, the best I see to do is to create a simple custom IP…… This is very easy and I will fully cover it in the videos.”
Very good news – thank you! I will re-check your page from time to time to look for this video.
-Manfred
Hi Dr. Sadri,
Thank you for your training videos.
I am working on a project which uses a core that is supposed to be connected to Altera Avalon bus in memory mapped mode (including: Address[31:0], Din[31:0], Dout[31:0],Wr_en, Rd_en signals). But i dont have access to altera boards and i have to port this design to Microblaze PLB bus on a Xilinx spartan 3 FPGA.
Now the question is: “Is there any suitable (and of course simple!) xilinx alternative for avalon bus?”
Thanks in advance!
-Mahmoud
Hi Sadri
I developed a custom IP using vivado HLS with top function directive set as axilite and input and output variables passed as arguments to the top function set as axi stream.
I would like to connect to Microblaze processor to pass input to the IP and output can be viewed on ila. How can I do that and which interface I need to add in between for the same.
that is very straight forward. hls gives you the prepared design as a packaged ip and you directly put that in your block design in vivado.
In our design, we won t need the AXI-Streaming status and control ports which are used to transmit extra information alongside the data stream.
Hello, I am doing project which involves image filtering, so my module takes 3 pixel one by one, does some processing and at each pixel input, state of module change at rising edge of clock. But now i want to package it as AXI Lite slave, So where should i connect the clock of my module so that each time i write slv register of AXI slave the clock of my module gets a rising edge(so that state change with each write of slave register of AXI).
I am new to this field and still an undergraduate student. Any help will be appreciated.
i did not really understand what you want to do however, just one advice, use only one single clock signal for your axi slave interface.