Estimation of power consumption of an integrated circuit at RT level can be handy since it allows designers to obtain an approximate and yet accurate enough estimate on total power consumption of their design in a very short time.

Basically, the designer runs the logic simulation for his pure RTL design and obtains the switching activity statistics for his circuit. The test bench developed by the designer for the logic simulation is indeed the workload imposed to the circuit and power will be estimated for this specific workload.

In this writing I go through the details of how power estimation at RT level can be done using the Synopsys Design Compiler environment. During my descriptions I suppose that Synopsys VCS is used for logic simulation.

 Logic Simulation and Obtaining Switching Activity Statistics:

Suppose that the top level module of the developed RTL is called : AXI_OpenRISC_top

And we have developed a test bench, in which we have instantiated the AXI_OpenRISC_top unit and we have also created the required logic to stress this unit. Suppose that the name of the test bench module is : AXI_OpenRISC_testbench

Obviously, for the synopsys VCS to capture all of the waveforms of the design, one section of the AXI_OpenRISC_testbench will contain the following lines (in Verilog):

initial begin
        $vcdpluson;
        #200000
        $finish;
        $vcdplusclose;
end

Then we have a Makefile, which uses the Synopsys VCS, compiles the design, performs the simulation and then uses the generated VCD files to prepare the main circuit switching activity statistics. Here is a simplified Makefile:

simv:
        vcs -debug_all -full64 -PP +v2k -timescale=1ns/1ps +neg_tchk \
        +systemverilogext+sv +incdir+../RTL/includes \
        ../RTL/ulpcluster/AXI_OpenRISC_top.v \
        ../simRTL/AXI_OpenRISC_testbench.v 

saif: simv 
	./simv
	vcd2saif -64 -input vcdplus.vpd -output activity.saif

As you can see the Makefile introduces two targets: simv and saif. The simv target compiles the RTL and builds the main simulation executable file. Then the saif target first performs the logic simulation by running simv executable. The output of logic simulation is stored in a vpd file. The vcd2saif then reads the vpd file, and calculates the averaged switching activity for each element in the RTL. The generated saif file will then be given to the synthesis tool (Design Compiler) for estimating power at RTL.

Power Estimation at RTL using Design Compiler:

To perform accurate RT level power estimation, you run the dc_shell in topographical mode (with -topo). Furthermore you inform the synthesis tool at the time of synthesis that later you want to perform RTL power estimation by using the switching activity statistics obtained from pure RTL simulation.

In order to do that, in your synthesis script, after all of the libraries are loaded, design is read in and eleborated, and timing constraints are defined, just before you issue the compile_ultra command, you need to add these two lines: 

saif_map -start 
set_power_prediction

Then you go through compile_ultra, and after that you store all of the results. The synthesized design can be saved in either verilog or ddc format. I usually save it in both of the formats.

As a result, your synthesis TCL script will be some thing like the following. 

# load standard cell libraries 
source script_for_std_cell_setup.tcl
set_tlu_plus_files ...

# Then create your milkyway database
define_design_lib WORK -path ./work;

# create milky way database 
set mw_design_library name_of_your_milkyway

create_mw_lib -technology $technology_file -mw_reference_library $reference_lib $mw_design_library 
open_mw_lib $mw_design_library

check_tlu_plus_files
check_library

# read the RTL, set additional configuration flags, elaborate the design
set verilogout_no_tri true
set hdlin_enable_presto_for_dw true

source rtl_source_read_script.dc  

elaborate AXI_OpenRISC_top
set_fix_multiple_port_nets -all AXI_OpenRISC_top

# create the set of required timing constraints. 
create_clock -name "clk" -period ......
group_path -name ....
group_path -name ....
set_critical_range ....

# make sure the design is linked
link

# enable power calculation 
saif_map -start 
set_power_prediction

# compile the design
compile_ultra -no_autoungroup 

# save the outputs 
write_milkyway -output -overwrite name_of_your_design

write -format verilog -hierarchy -output file_name.v
write -format ddc -hierarchy -output file_name.ddc

change_names -rules verilog -hierarchy

write -format verilog -hierarchy -output file_name_2.v
write -format ddc -hierarchy -output file_name_2.ddc
write_sdc file_name_2.sdc

# then finally you generate what ever type of report you want.

Having the synthesized design in hand, we can go forward and load the switching activity statistics and estimate power at RTL. The script required to perform this operation looks like the following:

# load the standard cell lib
# define tlu plus files and ...

read_ddc synthesized_design.ddc 

set_power_prediction

# add commands here to define clocks and ...

# reading the switching activity file and reporing power 
read_saif -input saif_file_name.saif -instance_name AXI_OpenRISC_testbench/AXI_OpenRISC_topIns

report_power -analysis_effort high > output_power_report_log.txt 

# also store other types of power report, which give you more details of the power consumption of your cicuit , e.g.
report_power -analysis_effort high -hierarchy -levels 2 > output_log_file.txt

# and then a timing report is always very welcome
report_timing -path_type full -max_paths 10 -significant_digits 5 > timing_power_report.txt

Here is a portion of generated power report at RTL for our AXI OpenRISC design. 

Operating Conditions: NCCOM   Library: tcbn40lpbwplvttc_ccs
Wire Load Model Mode: Inactive.


Global Operating Voltage = 1.1  
Power-specific unit information :
    Voltage Units = 1V
    Capacitance Units = 1.000000pf
    Time Units = 1ns
    Dynamic Power Units = 1mW    (derived from V,C,T units)
    Leakage Power Units = 1nW

Information: Reporting correlated power. (PWR-620)

--------------------------------------------------------------------------------
                                       Switch   Int      Leak     Total
Hierarchy                              Power    Power    Power    Power    %
--------------------------------------------------------------------------------
AXI_OpenRISC_top                          7.940   29.879 6.49e+04   37.884 100.0
CLOCK_TREE_EST                            7.835    2.237  825.822   10.072  26.6
  ulpcluster_inst (AXI_OpenRISC_NB_CORES1_ADDR_WIDTH32_ADDR_WIDTH_INTERNAL32_DATA_WIDTH32)
                                          0.105   27.642 6.41e+04   27.812  73.4
    WB3_to_AXI4_inst_0 (WB3_to_AXI4_00000000_16_1_32_32_1_1_1_1_1)
                                       5.02e-02    0.294  424.584    0.344   0.9
      WB3_to_AXI4_M00_AXI_inst (WB3_to_AXI4_M00_AXI_00000000_16_1_32_32_1_1_1_1_1)
                                       5.02e-02    0.294  424.584    0.344   0.9
.
.
.
          or1200_ic_ram (or1200_ic_ram_FLIPWELL0)
                                       1.66e-03   21.789 4.33e+04   21.833  57.6
            ic_ram_odd (or1200_spram_128x32_1)
                                       1.46e-03   10.875 2.27e+04   10.900  28.8
            ic_ram_even (or1200_spram_128x32_0)
                                       1.91e-04   10.913 2.06e+04   10.934  28.9
          or1200_ic_fsm (or1200_ic_fsm)
                                       2.86e-06 9.36e-02  145.349 9.37e-02   0.2
        or1200_immu_top (or1200_immu_top)
                                       4.79e-05    0.140  337.935    0.140   0.4
        iwb_biu (or1200_wb_biu64_bl4)  2.99e-04    0.117  219.600    0.117   0.3
1

You can perform various types of analysis using these power and timing reports. Once you found the power consumption of your circuit at desirable limits, you go ahead to the rest of the flow.